This is octal D type transparent Latch. When the LATCH ENABLE(LE) input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.